​AMD’s Next-Gen EPYC “Venice” CPUs to Utilize TSMC’s 2nm Process; 5th Gen EPYC Validated at TSMC Arizona​

​AMD's Next-Gen EPYC "Venice" CPUs to Utilize TSMC's 2nm Process; 5th Gen EPYC Validated at TSMC Arizona​

Advanced Micro Devices (AMD) has announced a significant milestone in its high-performance computing (HPC) roadmap: the upcoming EPYC “Venice” processors will be the first HPC products manufactured using Taiwan Semiconductor Manufacturing Company’s (TSMC) advanced 2-nanometer (N2) process technology. Additionally, AMD has successfully validated its 5th Generation EPYC CPUs at TSMC’s new fabrication facility in Arizona, …

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